UARTx_C4 field descriptions (continued)Field Description5M1010-bit Mode selectCauses a tenth, non-memory mapped bit to be part of the serial transmission. This tenth bit is generatedand interpreted as a parity bit. If M10 is set, then both C1[M] and C1[PE] must also be set. This field mustbe cleared when C7816[ISO7816E] is set/enabled.See Data format (non ISO-7816) for more information.0 The parity bit is the ninth bit in the serial transmission.1 The parity bit is the tenth bit in the serial transmission.BRFA Baud Rate Fine AdjustThis bit field is used to add more timing resolution to the average baud frequency, in increments of 1/32.See Baud rate generation for more information.38.4.12 UART Control Register 5 (UARTx_C5)Address: 4006_C000h base + Bh offset = 4006_C00BhBit 7 6 5 4 3 2 1 0Read TDMAS 0 RDMAS 0 0WriteReset 0 0 0 0 0 0 0 0UARTx_C5 field descriptionsField Description7TDMASTransmitter DMA SelectConfigures the transmit data register empty flag, S1[TDRE], to generate interrupt or DMA requests ifC2[TIE] is set.NOTE: • If C2[TIE] is cleared, TDRE DMA and TDRE interrupt request signals are not assertedwhen the TDRE flag is set, regardless of the state of TDMAS.• If C2[TIE] and TDMAS are both set, then C2[TCIE] must be cleared, and D must not bewritten unless a DMA request is being serviced.0 If C2[TIE] is set and the S1[TDRE] flag is set, the TDRE interrupt request signal is asserted to requestinterrupt service.1 If C2[TIE] is set and the S1[TDRE] flag is set, the TDRE DMA request signal is asserted to request aDMA transfer.6ReservedThis field is reserved.This read-only field is reserved and always has the value 0.5RDMASReceiver Full DMA SelectConfigures the receiver data register full flag, S1[RDRF], to generate interrupt or DMA requests if C2[RIE]is set.NOTE: If C2[RIE] is cleared, and S1[RDRF] is set, the RDRF DMA and RDFR interrupt request signalsare not asserted, regardless of the state of RDMAS.Table continues on the next page...Chapter 38 Universal Asynchronous Receiver/Transmitter(UART)KL27 Sub-Family Reference Manual , Rev. 5, 01/2016Freescale Semiconductor, Inc. 695
