GPIO memory map (continued)Absoluteaddress(hex)Register name Width(in bits) Access Reset value Section/page400F_F0C4 Port Set Output Register (GPIOD_PSOR) 32W(alwaysreads 0)0000_0000h 41.3.2/826400F_F0C8 Port Clear Output Register (GPIOD_PCOR) 32W(alwaysreads 0)0000_0000h 41.3.3/826400F_F0CC Port Toggle Output Register (GPIOD_PTOR) 32W(alwaysreads 0)0000_0000h 41.3.4/827400F_F0D0 Port Data Input Register (GPIOD_PDIR) 32 R 0000_0000h 41.3.5/827400F_F0D4 Port Data Direction Register (GPIOD_PDDR) 32 R/W 0000_0000h 41.3.6/828400F_F100 Port Data Output Register (GPIOE_PDOR) 32 R/W 0000_0000h 41.3.1/825400F_F104 Port Set Output Register (GPIOE_PSOR) 32W(alwaysreads 0)0000_0000h 41.3.2/826400F_F108 Port Clear Output Register (GPIOE_PCOR) 32W(alwaysreads 0)0000_0000h 41.3.3/826400F_F10C Port Toggle Output Register (GPIOE_PTOR) 32W(alwaysreads 0)0000_0000h 41.3.4/827400F_F110 Port Data Input Register (GPIOE_PDIR) 32 R 0000_0000h 41.3.5/827400F_F114 Port Data Direction Register (GPIOE_PDDR) 32 R/W 0000_0000h 41.3.6/82841.3.1 Port Data Output Register (GPIOx_PDOR)This register configures the logic levels that are driven on each general-purpose outputpins.NOTEDo not modify pin configuration registers associated with pinsnot available in your selected package. All unbonded pins notavailable in your package will default to DISABLE state forlowest power consumption.Address: Base address + 0h offsetBit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0R PDOWReset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0Chapter 41 General-Purpose Input/Output (GPIO)KL27 Sub-Family Reference Manual , Rev. 5, 01/2016Freescale Semiconductor, Inc. 825
