37.3.1 LPUART Baud Rate Register (LPUARTx_BAUD)Address: Base address + 0h offsetBit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16RMAEN1MAEN2M10 OSRTDMAE 0RDMAE 0MATCFGBOTHEDGERESYNCDISWReset 0 0 0 0 1 1 1 1 0 0 0 0 0 0 0 0Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0RLBKDIERXEDGIESBNS SBRWReset 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0LPUARTx_BAUD field descriptionsField Description31MAEN1Match Address Mode Enable 10 Normal operation.1 Enables automatic address matching or data matching mode for MATCH[MA1].30MAEN2Match Address Mode Enable 20 Normal operation.1 Enables automatic address matching or data matching mode for MATCH[MA2].29M1010-bit Mode selectThe M10 bit causes a tenth bit to be part of the serial transmission. This bit should only be changed whenthe transmitter and receiver are both disabled.0 Receiver and transmitter use 8-bit or 9-bit data characters.1 Receiver and transmitter use 10-bit data characters.28–24OSROversampling RatioThis field configures the oversampling ratio for the receiver between 4x (00011) and 32x (11111). Writingan invalid oversampling ratio (for example, a value not between 4x and 32x) will default to anoversampling ratio of 16 (01111). The OSR field should only be changed when the transmitter andreceiver are both disabled. Note that the oversampling ratio = OSR + 1.23TDMAETransmitter DMA EnableTDMAE configures the transmit data register empty flag, LPUART_STAT[TDRE], to generate a DMArequest.0 DMA request disabled.1 DMA request enabled.Table continues on the next page...Register definitionKL27 Sub-Family Reference Manual , Rev. 5, 01/2016652 Freescale Semiconductor, Inc.
