Section number Title Page3.1 ARM Cortex-M0+ core introduction............................................................................................................................ 493.1.1 Buses, interconnects, and interfaces.............................................................................................................. 493.1.2 System tick timer........................................................................................................................................... 493.1.3 Debug facilities.............................................................................................................................................. 493.1.4 Core privilege levels...................................................................................................................................... 503.2 Nested vectored interrupt controller (NVIC) ...............................................................................................................503.2.1 Interrupt priority levels.................................................................................................................................. 503.2.2 Non-maskable interrupt..................................................................................................................................503.2.3 Interrupt channel assignments........................................................................................................................503.3 AWIC introduction....................................................................................................................................................... 533.3.1 Wake-up sources............................................................................................................................................ 53Chapter 4Memory Map4.1 Introduction...................................................................................................................................................................554.2 Flash memory............................................................................................................................................................... 554.2.1 Flash memory map.........................................................................................................................................554.2.2 Flash security................................................................................................................................................. 564.2.3 Flash modes....................................................................................................................................................564.2.4 Erase all flash contents...................................................................................................................................564.2.5 FTFA_FOPT register..................................................................................................................................... 574.3 SRAM........................................................................................................................................................................... 574.3.1 SRAM sizes....................................................................................................................................................574.3.2 SRAM ranges................................................................................................................................................. 574.3.3 SRAM retention in low power modes............................................................................................................584.4 System Register file...................................................................................................................................................... 584.5 System memory map.....................................................................................................................................................594.6 Bit Manipulation Engine...............................................................................................................................................604.7 Peripheral bridge (AIPS-Lite) memory map.................................................................................................................604.7.1 Read-after-write sequence and required serialization of memory operations................................................60KL27 Sub-Family Reference Manual , Rev. 5, 01/20164 Freescale Semiconductor, Inc.
