33.5.21 USB Transceiver Control register 0 (USBx_USBTRC0)Includes signals for basic operation of the on-chip USB Full Speed transceiver andconfiguration of the USB data connection that are not otherwise included in the USB FullSpeed controller registers.Address: 4007_2000h base + 10Ch offset = 4007_210ChBit 7 6 5 4Read USBRESMEN 0Write USBRESET 1Reset 0 0 0 0Bit 3 2 1 0Read 0 USB_CLK_RECOVERY_INT SYNC_DET USB_RESUME_INTWriteReset 0 0 0 0USBx_USBTRC0 field descriptionsField Description7USBRESETUSB ResetGenerates a hard reset to USB. After this bit is set and the reset occurs, this bit is automatically cleared.NOTE: This bit is always read as zero. Wait two USB clock cycles after setting this bit.0 Normal USB module operation.1 Returns the USB module to its reset state.6ReservedThis field is reserved.NOTE: Software must set this bit to 1b.5USBRESMENAsynchronous Resume Interrupt EnableThis bit, when set, allows the USB module to send an asynchronous wakeup event to the MCU upondetection of resume signaling on the USB bus. The MCU then re-enables clocks to the USB module. It isused for low-power suspend mode when USB module clocks are stopped or the USB transceiver is inSuspend mode. Async wakeup only works in device mode.0 USB asynchronous wakeup from suspend mode disabled.1 USB asynchronous wakeup from suspend mode enabled. The asynchronous resume interrupt differsfrom the synchronous resume interrupt in that it asynchronously detects K-state using the unfilteredstate of the D+ and D– pins. This interrupt should only be enabled when the Transceiver issuspended.4–3ReservedThis field is reserved.This read-only field is reserved and always has the value 0.Table continues on the next page...Chapter 33 Universal Serial Bus (USB) FS SubsystemKL27 Sub-Family Reference Manual , Rev. 5, 01/2016Freescale Semiconductor, Inc. 557
