PIT_MCR field descriptions (continued)Field Description0FRZFreezeAllows the timers to be stopped when the device enters the Debug mode.0 Timers continue to run in Debug mode.1 Timers are stopped in Debug mode.30.4.2 PIT Upper Lifetime Timer Register (PIT_LTMR64H)This register is intended for applications that chain timer 0 and timer 1 to build a 64-bitlifetimer.Access: User read onlyAddress: 4003_7000h base + E0h offset = 4003_70E0hBit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0R LTHWReset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0PIT_LTMR64H field descriptionsField DescriptionLTH Life Timer valueShows the timer value of timer 1. If this register is read at a time t1, LTMR64L shows the value of timer 0at time t1.30.4.3 PIT Lower Lifetime Timer Register (PIT_LTMR64L)This register is intended for applications that chain timer 0 and timer 1 to build a 64-bitlifetimer.To use LTMR64H and LTMR64L, timer 0 and timer 1 need to be chained. To obtain thecorrect value, first read LTMR64H and then LTMR64L. LTMR64H will have the valueof CVAL1 at the time of the first access, LTMR64L will have the value of CVAL0 at thetime of the first access, therefore the application does not need to worry about carry-overeffects of the running counter.Access: User read onlyChapter 30 Periodic Interrupt Timer (PIT)KL27 Sub-Family Reference Manual , Rev. 5, 01/2016Freescale Semiconductor, Inc. 491
