NoteCare must be taken when expecting data from a master whilethe slave is in a Wait mode or a Stop mode where the peripheralbus clock is stopped but internal logic states are retained. Eventhough the shift register continues to operate, the rest of the SPIis shut down (that is, an SPRF interrupt is not generated until anexit from Stop or Wait mode). Also, the data from the shiftregister is not copied into the SPIx_DH:SPIx_DL registers untilafter the slave SPI has exited Wait or Stop mode. An SPRF flagand SPIx_DH:SPIx_DL copy is only generated if Wait mode isentered or exited during a transmission. If the slave enters Waitmode in idle mode and exits Wait mode in idle mode, neither anSPRF nor a SPIx_DH:SPIx_DL copy occurs.35.5.11.3 SPI in Stop modeOperation in a Stop mode where the peripheral bus clock is stopped but internal logicstates are retained depends on the SPI system. The Stop mode does not depend onC2[SPISWAI]. Upon entry to this type of stop mode, the SPI module clock is disabled(held high or low).• If the SPI is in master mode and exchanging data when the CPU enters the Stopmode, the transmission is frozen until the CPU exits stop mode. After the exit fromstop mode, data to and from the external SPI is exchanged correctly.• In slave mode, the SPI remains synchronized with the master.The SPI is completely disabled in a stop mode where the peripheral bus clock is stoppedand internal logic states are not retained. After an exit from this type of stop mode, allregisters are reset to their default values, and the SPI module must be reinitialized.35.5.12 ResetThe reset values of registers and signals are described in the Memory Map and RegisterDescriptions content, which details the registers and their bitfields.• If a data transmission occurs in slave mode after a reset without a write toSPIx_DH:SPIx_DL, the transmission consists of "garbage" or the data last receivedfrom the master before the reset.• Reading from SPIx_DH:SPIx_DL after reset always returns zeros.Functional descriptionKL27 Sub-Family Reference Manual , Rev. 5, 01/2016602 Freescale Semiconductor, Inc.
