32.3.6 RTC Status Register (RTC_SR)Address: 4003_D000h base + 14h offset = 4003_D014hBit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16R 0WReset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0R 0 TCE 0 TAF TOF TIFWReset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1RTC_SR field descriptionsField Description31–5ReservedThis field is reserved.This read-only field is reserved and always has the value 0.4TCETime Counter EnableWhen time counter is disabled the TSR register and TPR register are writeable, but do not increment.When time counter is enabled the TSR register and TPR register are not writeable, but increment.0 Time counter is disabled.1 Time counter is enabled.3ReservedThis field is reserved.This read-only field is reserved and always has the value 0.2TAFTime Alarm FlagTime alarm flag is set when the TAR[TAR] equals the TSR[TSR] and the TSR[TSR] increments. This bit iscleared by writing the TAR register.0 Time alarm has not occurred.1 Time alarm has occurred.1TOFTime Overflow FlagTime overflow flag is set when the time counter is enabled and overflows. The TSR and TPR do notincrement and read as zero when this bit is set. This bit is cleared by writing the TSR register when thetime counter is disabled.0 Time overflow has not occurred.1 Time overflow has occurred and time counter is read as zero.0TIFTime Invalid FlagThe time invalid flag is set on POR or software reset. The TSR and TPR do not increment and read aszero when this bit is set. This bit is cleared by writing the TSR register when the time counter is disabled.0 Time is valid.1 Time is invalid and time counter is read as zero.Register definitionKL27 Sub-Family Reference Manual , Rev. 5, 01/2016520 Freescale Semiconductor, Inc.
