The CNR will increment each time the glitch filter output asserts. In Pulse Counter mode,the maximum rate at which the CNR can increment is once every 22 to 216 prescalerclock edges. When first enabled, the glitch filter will wait an additional one or twoprescaler clock edges due to synchronization logic.31.5.3.4 Glitch filter bypassedIn Pulse Counter mode, when the glitch filter is bypassed, the selected input sourceincrements the CNR every time it asserts. Before the LPTMR is first enabled, the selectedinput source is forced to be asserted. This prevents the CNR from incrementing if theselected input source is already asserted when the LPTMR is first enabled.31.5.4 LPTMR compareWhen the CNR equals the value of the CMR and increments, the following events occur:• CSR[TCF] is set.• LPTMR interrupt is generated if CSR[TIE] is also set.• LPTMR hardware trigger is generated.• CNR is reset if CSR[TFC] is clear.When the LPTMR is enabled, the CMR can be altered only when CSR[TCF] is set. Whenupdating the CMR, the CMR must be written and CSR[TCF] must be cleared before theLPTMR counter has incremented past the new LPTMR compare value.31.5.5 LPTMR counterThe CNR increments by one on every:• Prescaler clock in Time Counter mode with prescaler bypassed• Prescaler output in Time Counter mode with prescaler enabled• Input source assertion in Pulse Counter mode with glitch filter bypassed• Glitch filter output in Pulse Counter mode with glitch filter enabledThe CNR is reset when the LPTMR is disabled or if the counter register overflows. IfCSR[TFC] is cleared, then the CNR is also reset whenever CSR[TCF] is set.The CNR continues incrementing when the core is halted in Debug mode whenconfigured for Pulse Counter mode, the CNR will stop incrementing when the core ishalted in Debug mode when configured for Time Counter mode.Functional descriptionKL27 Sub-Family Reference Manual , Rev. 5, 01/2016510 Freescale Semiconductor, Inc.
