In Stop mode, if the Transmitter Stop Enable (TCSR[STOPE]) bit is clear, the transmitteris disabled after completing the current transmit frame, and, if the Receiver Stop Enable(RCSR[STOPE]) bit is clear, the receiver is disabled after completing the current receiveframe. Entry into Stop mode is prevented–not acknowledged–while waiting for thetransmitter and receiver to be disabled at the end of the current frame.40.2.3.3 Low-leakage modesWhen entering low-leakage modes, the Stop Enable (TCSR[STOPE] andRCSR[STOPE]) bits are ignored and the SAI is disabled after completing the currenttransmit and receive Frames. Entry into stop mode is prevented (not acknowledged)while waiting for the transmitter and receiver to be disabled at the end of the currentframe.40.2.3.4 Debug modeIn Debug mode, the SAI transmitter and/or receiver can continue operating provided theDebug Enable bit is set. When TCSR[DBGE] or RCSR[DBGE] bit is clear and Debugmode is entered, the SAI is disabled after completing the current transmit or receiveframe. The transmitter and receiver bit clocks are not affected by Debug mode.40.3 External signalsName Function I/OSAI_TX_BCLK Transmit Bit Clock. The bit clock is an input whenexternally generated and an output wheninternally generated.I/OSAI_TX_SYNC Transmit Frame Sync. The frame sync is an inputsampled synchronously by the bit clock whenexternally generated and an output generatedsynchronously by the bit clock when internallygenerated.I/OSAI_TX_DATA Transmit Data. The transmit data is generatedsynchronously by the bit clock and is tristatedwhenever not transmitting a word.OSAI_RX_BCLK Receive Bit Clock. The bit clock is an input whenexternally generated and an output wheninternally generated.I/OSAI_RX_SYNC Receive Frame Sync. The frame sync is an inputsampled synchronously by the bit clock whenI/OTable continues on the next page...External signalsKL27 Sub-Family Reference Manual , Rev. 5, 01/2016790 Freescale Semiconductor, Inc.
