40.4.2 SAI Transmit Configuration 2 Register (I2Sx_TCR2)This register must not be altered when TCSR[TE] is set.Address: 4002_F000h base + 8h offset = 4002_F008hBit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16R SYNC BCS BCI MSEL BCP BCD 0WReset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0R 0 DIVWReset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0I2Sx_TCR2 field descriptionsField Description31–30SYNCSynchronous ModeConfigures between asynchronous and synchronous modes of operation. When configured for asynchronous mode of operation, the receiver must be configured for asynchronous operation.00 Asynchronous mode.01 Synchronous with receiver.10 Synchronous with another SAI transmitter.11 Synchronous with another SAI receiver.29BCSBit Clock SwapThis field swaps the bit clock used by the transmitter. When the transmitter is configured in asynchronousmode and this bit is set, the transmitter is clocked by the receiver bit clock (SAI_RX_BCLK). This allowsthe transmitter and receiver to share the same bit clock, but the transmitter continues to use the transmitframe sync (SAI_TX_SYNC).When the transmitter is configured in synchronous mode, the transmitter BCS field and receiver BCS fieldmust be set to the same value. When both are set, the transmitter and receiver are both clocked by thetransmitter bit clock (SAI_TX_BCLK) but use the receiver frame sync (SAI_RX_SYNC).0 Use the normal bit clock source.1 Swap the bit clock source.28BCIBit Clock InputWhen this field is set and using an internally generated bit clock in either synchronous or asynchronousmode, the bit clock actually used by the transmitter is delayed by the pad output delay (the transmitter isclocked by the pad input as if the clock was externally generated). This has the effect of decreasing thedata input setup time, but increasing the data output valid time.The slave mode timing from the datasheet should be used for the transmitter when this bit is set. Insynchronous mode, this bit allows the transmitter to use the slave mode timing from the datasheet, whilethe receiver uses the master mode timing. This field has no effect when configured for an externallygenerated bit clock .0 No effect.1 Internal logic is clocked as if bit clock was externally generated.Table continues on the next page...Chapter 40 Synchronous Audio Interface (SAI)KL27 Sub-Family Reference Manual , Rev. 5, 01/2016Freescale Semiconductor, Inc. 795
