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NXP Semiconductors MKL04Z32VLC4 manuals

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MKL04Z32VLC4

Brand: NXP Semiconductors | Category: Microcontrollers
Table of contents
  1. Table Of Contents
  2. Table Of Contents
  3. Table Of Contents
  4. Table Of Contents
  5. Table Of Contents
  6. Table Of Contents
  7. Table Of Contents
  8. Table Of Contents
  9. Table Of Contents
  10. Table Of Contents
  11. Table Of Contents
  12. Table Of Contents
  13. Table Of Contents
  14. Table Of Contents
  15. Table Of Contents
  16. Table Of Contents
  17. Table Of Contents
  18. Table Of Contents
  19. Table Of Contents
  20. Table Of Contents
  21. Table Of Contents
  22. Table Of Contents
  23. Table Of Contents
  24. Table Of Contents
  25. Table Of Contents
  26. Overview
  27. Typographic notation
  29. KL04 Sub-Family Introduction
  30. Module functional categories
  31. System Modules
  32. Memories and Memory Interfaces
  33. Analog modules
  34. Communication interfaces
  35. Introduction
  36. KL04 Sub-Family Reference Manual, Rev. 3.1, November
  37. Analog reference options
  38. Core Modules
  39. Nested Vectored Interrupt Controller (NVIC) Configuration
  40. Asynchronous wake-up interrupt controller (AWIC) configuration
  42. System Mode Controller (SMC) Configuration
  43. Low-Leakage Wake-up Unit (LLWU) Configuration
  44. MCM Configuration
  45. Crossbar-Light Switch Configuration
  46. Peripheral Bridge Configuration
  47. DMA request multiplexer configuration
  48. DMA Controller Configuration
  49. Clock Modules
  50. OSC Configuration
  52. Flash Memory Controller Configuration
  54. Analog
  55. CMP Configuration
  56. Timers
  57. PIT Configuration
  58. Low-power timer configuration
  59. RTC configuration
  61. I2C Configuration
  62. Human-machine interfaces (HMI)
  63. Memory Map
  65. Flash Memory Map
  66. Alternate Non-Volatile IRC User Trim Description
  67. Peripheral bridge (AIPS-Lite) memory map
  69. Modules Restricted Access in User Mode
  72. Clock definitions
  73. Device clock summary
  74. Internal clocking requirements
  75. VLPR mode clocking
  76. PMC 1-kHz LPO clock
  77. LPTMR clocking
  78. UART clocking
  80. Power-on reset (POR)
  81. MCU Resets
  82. Reset Pin
  83. Debug resets
  84. Boot
  87. DMA Wakeup
  88. Compute Operation
  89. Peripheral Doze
  90. Clock Gating
  91. Entering and exiting power modes
  93. Security Interactions with Debug
  95. SWD status and control registers
  96. MDM-AP Control Register
  97. MDM-AP Status Register
  99. Micro Trace Buffer (MTB)
  102. Port control and interrupt module features
  104. KL04 Pinouts
  105. Module Signal Description Tables
  110. Modes of operation
  111. Detailed signal description
  113. Pin Control Register n (PORTx_PCRn)
  114. Global Pin Control Low Register (PORTx_GPCLR)
  115. Global Pin Control High Register (PORTx_GPCHR)
  116. Functional description
  117. Global pin control
  119. System Options Register 1 (SIM_SOPT1)
  120. System Options Register 2 (SIM_SOPT2)
  121. System Options Register 4 (SIM_SOPT4)
  122. System Options Register 5 (SIM_SOPT5)
  123. System Options Register 7 (SIM_SOPT7)
  124. System Device Identification Register (SIM_SDID)
  125. System Clock Gating Control Register 4 (SIM_SCGC4)
  126. System Clock Gating Control Register 5 (SIM_SCGC5)
  127. System Clock Gating Control Register 6 (SIM_SCGC6)
  128. System Clock Gating Control Register 7 (SIM_SCGC7)
  129. System Clock Divider Register 1 (SIM_CLKDIV1)
  130. Flash Configuration Register 1 (SIM_FCFG1)
  131. Flash Configuration Register 2 (SIM_FCFG2)
  132. Unique Identification Register Mid-High (SIM_UIDMH)
  134. Service COP Register (SIM_SRVCOP)
  137. Memory map and register descriptions
  138. Power Mode Control register (SMC_PMCTRL)
  139. Stop Control Register (SMC_STOPCTRL)
  140. Power Mode Status register (SMC_PMSTAT)
  142. Power mode entry/exit sequencing
  143. Run modes
  144. Wait modes
  145. Stop modes
  146. Debug in low power modes
  148. LVD reset operation
  150. Low Voltage Detect Status And Control 1 register (PMC_LVDSC1)
  151. Low Voltage Detect Status And Control 2 register (PMC_LVDSC2)
  152. Regulator Status And Control register (PMC_REGSC)
  155. Block diagram
  156. LLWU signal descriptions
  157. LLWU Pin Enable 1 register (LLWU_PE1)
  158. LLWU Pin Enable 2 register (LLWU_PE2)
  159. LLWU Module Enable register (LLWU_ME)
  160. LLWU Flag 1 register (LLWU_F1)
  161. LLWU Flag 3 register (LLWU_F3)
  162. LLWU Pin Filter 1 register (LLWU_FILT1)
  163. LLWU Pin Filter 2 register (LLWU_FILT2)
  165. LLS mode
  168. System Reset Status Register 1 (RCM_SRS1)
  169. Reset Pin Filter Control register (RCM_RPFC)
  170. Reset Pin Filter Width register (RCM_RPFW)
  174. Memory Map and Register Definition
  175. Additional Details on Decorated Addresses and GPIO Accesses
  176. Application Information
  178. Crossbar Switch (AXBS) Slave Configuration (MCM_PLASC)
  179. Crossbar Switch (AXBS) Master Configuration (MCM_PLAMC)
  180. Compute Operation Control Register (MCM_CPO)
  182. Features
  185. MTB_DWT Memory Map
  188. Arbitration
  189. Initialization/application information
  191. General operation
  194. External signal description
  196. DMA channels with periodic triggering capability
  197. Freescale Semiconductor, Inc
  198. DMA channels with no triggering capability
  206. DMA Transfer Overview
  207. Memory Map and Registers
  208. Source Address Register (DMA_SARn)
  209. Destination Address Register (DMA_DARn)
  210. DMA Status Register / Byte Count Register (DMA_DSR_BCRn)
  212. DMA Control Register (DMA_DCRn)
  217. Channel Initialization and Startup
  218. Dual-Address Data Transfer Mode
  219. Advanced Data Transfer Controls: Auto-Alignment
  220. Termination
  227. MCG Control 2 Register (MCG_C2)
  228. MCG Control 3 Register (MCG_C3)
  230. MCG Control 6 Register (MCG_C6)
  231. MCG Status and Control Register (MCG_SC)
  233. MCG Auto Trim Compare Value High Register (MCG_ATCVH)
  237. Low Power Bit Usage
  238. External Reference Clock
  240. Initialization / Application information
  242. Using a 32.768 kHz reference
  252. External Crystal / Resonator Connections
  253. External Clock Connections
  254. Memory Map/Register Definitions
  257. OSC Module Modes
  258. Counter
  259. Reset
  266. Glossary
  268. Flash Configuration Field Description
  269. Register Descriptions
  278. Flash Protection
  279. Flash Operation in Low-Power Modes
  280. Flash Reads and Ignored Writes
  285. Margin Read Commands
  286. Flash Command Description
  299. Security
  301. Reset Sequence
  305. Voltage Reference Select
  306. Analog Channel Inputs (ADx)
  307. ADC Status and Control Registers 1 (ADCx_SC1n)
  310. ADC Configuration Register 1 (ADCx_CFG1)
  312. ADC Configuration Register 2 (ADCx_CFG2)
  313. ADC Data Result Register (ADCx_Rn)
  314. Compare Value Registers (ADCx_CVn)
  315. Status and Control Register 2 (ADCx_SC2)
  317. Status and Control Register 3 (ADCx_SC3)
  318. ADC Offset Correction Register (ADCx_OFS)
  319. ADC Plus-Side Gain Register (ADCx_PG)
  320. ADC Plus-Side General Calibration Value Register (ADCx_CLPS)
  321. ADC Plus-Side General Calibration Value Register (ADCx_CLP3)
  322. ADC Plus-Side General Calibration Value Register (ADCx_CLP1)
  324. Voltage reference selection
  325. Conversion control
  332. Automatic compare function
  334. Calibration function
  336. Temperature sensor
  337. MCU wait mode operation
  338. MCU Low-Power Stop mode operation
  339. Initialization information
  343. Sources of error
  349. bit DAC key features
  350. ANMUX key features
  351. CMP block diagram
  354. CMP Control Register 1 (CMPx_CR1)
  356. CMP Filter Period Register (CMPx_FPR)
  357. DAC Control Register (CMPx_DACCR)
  358. MUX Control Register (CMPx_MUXCR)
  368. Power modes
  369. Startup and operation
  372. CMP interrupts
  373. Digital-to-analog converter
  374. Voltage reference source select
  378. TPM Signal Descriptions
  379. TPM_EXTCLK — TPM External Clock
  381. Status and Control (TPMx_SC)
  382. Counter (TPMx_CNT)
  383. Modulo (TPMx_MOD)
  384. Channel (n) Status and Control (TPMx_CnSC)
  386. Channel (n) Value (TPMx_CnV)
  388. Configuration (TPMx_CONF)
  391. Prescaler
  393. Input Capture Mode
  394. Output Compare Mode
  396. Edge-Aligned PWM (EPWM) Mode
  397. Center-Aligned PWM (CPWM) Mode
  399. Registers Updated from Write Buffers
  400. Reset Overview
  404. Memory map/register description
  406. PIT Upper Lifetime Timer Register (PIT_LTMR64H)
  407. Timer Load Value Register (PIT_LDVALn)
  408. Timer Control Register (PIT_TCTRLn)
  409. Timer Flag Register (PIT_TFLGn)
  411. Interrupts
  413. Example configuration for the lifetime timer
  417. LPTMR signal descriptions
  418. Low Power Timer Control Status Register (LPTMRx_CSR)
  419. Low Power Timer Prescale Register (LPTMRx_PSR)
  421. Low Power Timer Compare Register (LPTMRx_CMR)
  424. LPTMR compare
  425. LPTMR hardware trigger
  428. RTC Time Seconds Register (RTC_TSR)
  429. RTC Time Alarm Register (RTC_TAR)
  430. RTC Control Register (RTC_CR)
  432. RTC Status Register (RTC_SR)
  433. RTC Lock Register (RTC_LR)
  434. RTC Interrupt Enable Register (RTC_IER)
  436. Time counter
  437. Time alarm
  438. Update mode
  442. Block Diagrams
  445. SPSCK — SPI Serial Clock
  448. SPI control register 2 (SPIx_C2)
  449. SPI baud rate register (SPIx_BR)
  450. SPI status register (SPIx_S)
  451. SPI data register (SPIx_D)
  452. SPI match register (SPIx_M)
  455. Slave Mode
  456. SPI Transmission by DMA
  458. SPI Clock Formats
  461. SPI Baud Rate Generation
  463. Error Conditions
  464. Low Power Mode Options
  468. Pseudo-Code Example
  475. I2C Address Register 1 (I2Cx_A1)
  476. I2C Frequency Divider register (I2Cx_F)
  477. I2C Control Register 1 (I2Cx_C1)
  478. I2C Status register (I2Cx_S)
  480. I2C Data I/O register (I2Cx_D)
  481. I2C Control Register 2 (I2Cx_C2)
  482. I2C Programmable Input Glitch Filter register (I2Cx_FLT)
  483. I2C Range Address register (I2Cx_RA)
  484. I2C SMBus Control and Status register (I2Cx_SMB)
  485. I2C Address Register 2 (I2Cx_A2)
  486. I2C SCL Low Timeout Register High (I2Cx_SLTH)
  487. I2C protocol
  492. bit address
  493. Address matching
  494. System management bus specification
  497. Resets
  499. Programmable input glitch filter
  500. Address matching wakeup
  507. Register definition
  508. UART Baud Rate Register High (UARTx_BDH)
  509. UART Baud Rate Register Low (UARTx_BDL)
  511. UART Control Register 2 (UARTx_C2)
  512. UART Status Register 1 (UARTx_S1)
  514. UART Status Register 2 (UARTx_S2)
  516. UART Control Register 3 (UARTx_C3)
  517. UART Data Register (UARTx_D)
  518. UART Match Address Registers 1 (UARTx_MA1)
  519. UART Match Address Registers 2 (UARTx_MA2)
  520. UART Control Register 5 (UARTx_C5)
  523. Receiver functional description
  526. Additional UART functions
  528. Interrupts and status flags
  533. Port Data Output Register (GPIOx_PDOR)
  535. Port Toggle Output Register (GPIOx_PTOR)
  536. Port Data Direction Register (GPIOx_PDDR)
  537. Port Data Output Register (FGPIOx_PDOR)
  538. Port Clear Output Register (FGPIOx_PCOR)
  539. Port Data Input Register (FGPIOx_PDIR)
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