29.7.3 CMP Filter Period Register (CMPx_FPR)Address: 4007_3000h base + 2h offset = 4007_3002hBit 7 6 5 4 3 2 1 0Read FILT_PERWriteReset 0 0 0 0 0 0 0 0CMPx_FPR field descriptionsField Description7–0FILT_PERFilter Sample PeriodSpecifies the sampling period, in bus clock cycles, of the comparator output filter, when CR1[SE]=0.Setting FILT_PER to 0x0 disables the filter. Filter programming and latency details appear in theFunctional description.This field has no effect when CR1[SE]=1. In that case, the external SAMPLE signal is used to determinethe sampling period.29.7.4 CMP Status and Control Register (CMPx_SCR)Address: 4007_3000h base + 3h offset = 4007_3003hBit 7 6 5 4 3 2 1 0Read 0 DMAEN 0 IER IEF CFR CFF COUTWrite w1c w1cReset 0 0 0 0 0 0 0 0CMPx_SCR field descriptionsField Description7ReservedThis field is reserved.This read-only field is reserved and always has the value 0.6DMAENDMA Enable ControlEnables the DMA transfer triggered from the CMP module. When this field is set, a DMA request isasserted when CFR or CFF is set.0 DMA is disabled.1 DMA is enabled.5ReservedThis field is reserved.This read-only field is reserved and always has the value 0.4IERComparator Interrupt Enable RisingEnables the CFR interrupt from the CMP. When this field is set, an interrupt will be asserted when CFR isset.Table continues on the next page...Chapter 29 Comparator (CMP)KL04 Sub-Family Reference Manual, Rev. 3.1, November 2012Freescale Semiconductor, Inc. 471
