SPI0_C2 field descriptions (continued)Field Description0 DMA request for receive is disabled and interrupt from SPRF is allowed1 DMA request for receive is enabled and interrupt from SPRF is disabled1SPISWAISPI stop in wait modeThis bit is used for power conservation while the device is in wait mode.0 SPI clocks continue to operate in wait mode1 SPI clocks stop when the MCU enters wait mode0SPC0SPI pin control 0This bit enables bidirectional pin configurations.0 SPI uses separate pins for data input and data output (pin mode is normal).In master mode of operation: MISO is master in and MOSI is master out.In slave mode of operation: MISO is slave out and MOSI is slave in.1 SPI configured for single-wire bidirectional operation (pin mode is bidirectional).In master mode of operation: MISO is not used by SPI; MOSI is master in when BIDIROE is 0 ormaster I/O when BIDIROE is 1.In slave mode of operation: MISO is slave in when BIDIROE is 0 or slave I/O when BIDIROE is 1;MOSI is not used by SPI.34.3.3 SPI baud rate register (SPIx_BR)Use this register to set the prescaler and bit rate divisor for an SPI master. This registermay be read or written at any time.Address: 4007_6000h base + 2h offset = 4007_6002hBit 7 6 5 4 3 2 1 0Read 0 SPPR[2:0] SPR[3:0]WriteReset 0 0 0 0 0 0 0 0SPI0_BR field descriptionsField Description7ReservedThis field is reserved.This read-only field is reserved and always has the value 0.6–4SPPR[2:0]SPI baud rate prescale divisorThis 3-bit field selects one of eight divisors for the SPI baud rate prescaler. The input to this prescaler isthe bus rate clock (BUSCLK). The output of this prescaler drives the input of the SPI baud rate divider.Refer to the description of “SPI Baud Rate Generation” for details.000 Baud rate prescaler divisor is 1Table continues on the next page...Memory Map and Register DescriptionsKL04 Sub-Family Reference Manual, Rev. 3.1, November 2012564 Freescale Semiconductor, Inc.
