resulting DCO output frequency is 62.91 MHz at mid high-range. If C4[DRST_DRS] bitsare set to 2'b11, the multiplication factor is set to 2560, and the resulting DCO outputfrequency is 83.89 MHz at high-range.In FBI and FEI modes, setting C4[DMX32] bit is not recommended. If the internalreference is trimmed to a frequency above 32.768 kHz, the greater FLL multiplicationfactor could potentially push the microcontroller system clock out of specification anddamage the part.24.5.3 MCG mode switchingWhen switching between operational modes of the MCG, certain configuration bits mustbe changed in order to properly move from one mode to another. Each time any of thesebits are changed (C1[IREFS], C1[CLKS], C2[IRCS], or C2[EREFS0]), thecorresponding bits in the MCG status register (IREFST, CLKST, IRCST, or OSCINIT)must be checked before moving on in the application software.Additionally, care must be taken to ensure that the reference clock divider (C1[FRDIV])is set properly for the mode being switched to. For instance, in FEE mode, if using a4MHz crystal, C1[FRDIV] must be set to 3'b010 (divide-by-128) to devide the externalfrequency down to the required frequency between 31.25 and 39.0625 kHz.In FBE, FEE, FBI, and FEI modes, at any time, the application can switch the FLLmultiplication factor between 640, 1280, 1920, and 2560 with C4[DRST_DRS] bits.Writes to C4[DRST_DRS] bits will be ignored if C2[LP]=1.The table below shows MCGOUTCLK frequency calculations using C1[FRDIV]settingsfor each clock mode.Table 24-12. MCGOUTCLK Frequency Calculation OptionsClock Mode fMCGOUTCLK1 NoteFEI (FLL engaged internal) (fint * F) Typical fMCGOUTCLK = 21 MHzimmediately after reset.FEE (FLL engaged external) (fext / FLL_R) *F fext / FLL_R must be in the range of31.25 kHz to 39.0625 kHzFBE (FLL bypassed external) OSCCLK OSCCLK / FLL_R must be in therange of 31.25 kHz to 39.0625 kHzFBI (FLL bypassed internal) MCGIRCLK Selectable between slow and fastIRCBLPI (Bypassed low power internal) MCGIRCLK Selectable between slow and fastIRCBLPE (Bypassed low power external) OSCCLK1. FLL_R is the reference divider selected by the C1[FRDIV] bits, F is the FLL factor selected by C4[DRST_DRS] andC4[DMX32] bits.Initialization / Application informationKL04 Sub-Family Reference Manual, Rev. 3.1, November 2012358 Freescale Semiconductor, Inc.
