12.2.1 System Options Register 1 (SIM_SOPT1)NOTEThe SOPT1 register is only reset on POR or LVD.Address: 4004_7000h base + 0h offset = 4004_7000hBit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16R 0 OSC32KSEL 0WReset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0R 0WReset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0SIM_SOPT1 field descriptionsField Description31–20ReservedThis field is reserved.This read-only field is reserved and always has the value 0.19–18OSC32KSEL32K oscillator clock selectSelects the 32 kHz clock source (ERCLK32K) for RTC and LPTMR. This bit is reset only on POR/LVD.00 System oscillator (OSC32KCLK)01 Reserved10 RTC_CLKIN11 LPO 1kHz17–0ReservedThis field is reserved.This read-only field is reserved and always has the value 0.12.2.2 SOPT1 Configuration Register (SIM_SOPT1CFG)NOTEThe SOPT1CFG register is reset on System Reset not VLLS.Address: 4004_7000h base + 4h offset = 4004_7004hBit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0R 0 0WReset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0Chapter 12 System integration module (SIM)KL04 Sub-Family Reference Manual, Rev. 3.1, November 2012Freescale Semiconductor, Inc. 167
