UART memory map (continued)Absoluteaddress(hex)Register name Width(in bits) Access Reset value Section/page4006_A009 UART Match Address Registers 2 (UART0_MA2) 8 R/W 00h 36.2.10/6344006_A00A UART Control Register 4 (UART0_C4) 8 R/W 0Fh 36.2.11/6344006_A00B UART Control Register 5 (UART0_C5) 8 R/W 00h 36.2.12/63536.2.1 UART Baud Rate Register High (UARTx_BDH)This register, along with UART _BDL, controls the prescale divisor for UART baud rategeneration. The 13-bit baud rate setting [SBR12:SBR0] should only be updated when thetransmitter and receiver are both disabled.Address: 4006_A000h base + 0h offset = 4006_A000hBit 7 6 5 4 3 2 1 0Read LBKDIE RXEDGIE SBNS SBRWriteReset 0 0 0 0 0 0 0 0UARTx_BDH field descriptionsField Description7LBKDIELIN Break Detect Interrupt Enable (for LBKDIF)0 Hardware interrupts from UART _S2[LBKDIF] disabled (use polling).1 Hardware interrupt requested when UART _S2[LBKDIF] flag is 1.6RXEDGIERX Input Active Edge Interrupt Enable (for RXEDGIF)0 Hardware interrupts from UART _S2[RXEDGIF] disabled (use polling).1 Hardware interrupt requested when UART _S2[RXEDGIF] flag is 1.5SBNSStop Bit Number SelectSBNS determines whether data characters are one or two stop bits. This bit should only be changed whenthe transmitter and receiver are both disabled.0 One stop bit.1 Two stop bit.4–0SBRBaud Rate Modulo Divisor.The 13 bits in SBR[12:0] are referred to collectively as BR, and they set the modulo divide rate for thebaud rate generator. When BR is 1 - 8191, the baud rate equals baud clock / ((OSR+1) × BR).Chapter 36 Universal Asynchronous Receiver/Transmitter (UART0)KL04 Sub-Family Reference Manual, Rev. 3.1, November 2012Freescale Semiconductor, Inc. 623
