When entering VLLS, each I/O pin is latched as configured before executing VLLS.Because all digital logic in the MCU is powered off, all port and peripheral data is lostduring VLLS. This information must be restored before the ACKISO bit in the PMC isset.An asserted RESET pin will cause an exit from any VLLS mode, returning the device tonormal RUN mode. When exiting VLLS via the RESET pin, the PIN and WAKEUP bitsare set in the SRS0 register of the reset control module (RCM).13.4.6 Debug in low power modesWhen the MCU is secure, the device disables/limits debugger operation. When the MCUis unsecure, the ARM debugger can assert two power-up request signals:• System power up, via SYSPWR in the Debug Port Control/Stat register• Debug power up, via CDBGPWRUPREQ in the Debug Port Control/Stat registerWhen asserted while in RUN, WAIT, VLPR, or VLPW, the mode controller drives acorresponding acknowledge for each signal, that is, both CDBGPWRUPACK andCSYSPWRUPACK. When both requests are asserted, the mode controller handlesattempts to enter STOP and VLPS by entering an emulated stop state. In this emulatedstop state:• the regulator is in run regulation,• the MCG-generated clock source is enabled,• all system clocks, except the core clock, are disabled,• the debug module has access to core registers, and• access to the on-chip peripherals is blocked.No debug is available while the MCU is in LLS or VLLS modes. LLS is a state-retentionmode and all debug operation can continue after waking from LLS, even in cases wheresystem wakeup is due to a system reset event.Entering into a VLLS mode causes all of the debug controls and settings to be poweredoff. To give time to the debugger to sync with the MCU, the MDM AP Control Registerincludes a Very-Low-Leakage Debug Request (VLLDBGREQ) bit that is set to configurethe Reset Controller logic to hold the system in reset after the next recovery from a VLLSmode. This bit allows the debugger time to reinitialize the debug module before thedebug session continues.Chapter 13 System Mode Controller (SMC)KL04 Sub-Family Reference Manual, Rev. 3.1, November 2012Freescale Semiconductor, Inc. 207
