30.3.4 Channel (n) Status and Control (TPMx_CnSC)CnSC contains the channel-interrupt-status flag and control bits used to configure theinterrupt enable, channel configuration, and pin function. When switching from onechannel mode to a different channel mode, the channel must first be disabled and thismust be acknowledged in the LPTPM counter clock domain.Table 30-34. Mode, Edge, and Level SelectionCPWMS MSnB:MSnA ELSnB:ELSnA Mode ConfigurationX 00 00 None Channel disabledX 01/10/11 00 Software compare Pin not used for LPTPM0 00 01 Input capture Capture on Rising EdgeOnly10 Capture on FallingEdge Only11 Capture on Rising orFalling Edge01 01 Output compare Toggle Output onmatch10 Clear Output on match11 Set Output on match10 10 Edge-aligned PWM High-true pulses (clearOutput on match, setOutput on reload)X1 Low-true pulses (setOutput on match, clearOutput on reload)11 10 Output compare Pulse Output low onmatchX1 Pulse Output high onmatch1 10 10 Center-aligned PWM High-true pulses (clearOutput on match-up,set Output on match-down)X1 Low-true pulses (setOutput on match-up,clear Output on match-down)Address: Base address + Ch offset + (8d × i), where i=0d to 5dBit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16R 0WReset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0Chapter 30 Timer/PWM Module (TPM)KL04 Sub-Family Reference Manual, Rev. 3.1, November 2012Freescale Semiconductor, Inc. 499
