The transmitter output (UART_TX) idle state defaults to logic high, C3[TXINV] iscleared following reset. The transmitter output is inverted by setting C3[TXINV]. Thetransmitter is enabled by setting the C2[TE] bit. This queues a preamble character that isone full character frame of the idle state. The transmitter then remains idle until data isavailable in the transmit data buffer. Programs store data into the transmit data buffer bywriting to the UART data register.The central element of the UART transmitter is the transmit shift register that is 10-bit to13 bits long depending on the setting in the C1[M], C2[M10] and BDH[SBNS] controlbits. For the remainder of this section, assume C1[M], C2[M10] and BDH[SBNS] arecleared, selecting the normal 8-bit data mode. In 8-bit data mode, the shift register holds astart bit, eight data bits, and a stop bit. When the transmit shift register is available for anew UART character, the value waiting in the transmit data register is transferred to theshift register, synchronized with the baud rate clock, and the transmit data register empty(S1[TDRE]) status flag is set to indicate another character may be written to the transmitdata buffer at UART_D.If no new character is waiting in the transmit data buffer after a stop bit is shifted out theUART_TX pin, the transmitter sets the transmit complete flag and enters an idle mode,with UART_TX high, waiting for more characters to transmit.Writing 0 to C2[TE] does not immediately disable the transmitter. The current transmitactivity in progress must first be completed. This includes data characters in progress,queued idle characters, and queued break characters.36.3.2.1 Send break and queued idleThe UART_C2[SBK] bit sends break characters originally used to gain the attention ofold teletype receivers. Break characters are a full character time of logic 0, 10-bit to 12-bit times including the start and stop bits. A longer break of 13-bit times can be enabledby setting UART_S2[BRK13]. Normally, a program would wait for UART_S1[TDRE]to become set to indicate the last character of a message has moved to the transmitshifter, write 1, and then write 0 to the UART_C2[SBK] bit. This action queues a breakcharacter to be sent as soon as the shifter is available. If UART_C2[SBK] remains 1when the queued break moves into the shifter, synchronized to the baud rate clock, anadditional break character is queued. If the receiving device is another FreescaleSemiconductor UART, the break characters are received as 0s in all data bits and aframing error (UART_S1[FE] = 1) occurs.When idle-line wakeup is used, a full character time of idle (logic 1) is needed betweenmessages to wake up any sleeping receivers. Normally, a program would wait forUART_S1[TDRE] to become set to indicate the last character of a message has moved toChapter 36 Universal Asynchronous Receiver/Transmitter (UART0)KL04 Sub-Family Reference Manual, Rev. 3.1, November 2012Freescale Semiconductor, Inc. 637
