SPI0_BR field descriptions (continued)Field Description001 Baud rate prescaler divisor is 2010 Baud rate prescaler divisor is 3011 Baud rate prescaler divisor is 4100 Baud rate prescaler divisor is 5101 Baud rate prescaler divisor is 6110 Baud rate prescaler divisor is 7111 Baud rate prescaler divisor is 83–0SPR[3:0]SPI baud rate divisorThis 4-bit field selects one of nine divisors for the SPI baud rate divider. The input to this divider comesfrom the SPI baud rate prescaler. Refer to the description of “SPI Baud Rate Generation” for details.0000 Baud rate divisor is 20001 Baud rate divisor is 40010 Baud rate divisor is 80011 Baud rate divisor is 160100 Baud rate divisor is 320101 Baud rate divisor is 640110 Baud rate divisor is 1280111 Baud rate divisor is 2561000 Baud rate divisor is 512All others Reserved34.3.4 SPI status register (SPIx_S)This register contains read-only status bits. Writes have no meaning or effect.NOTEBits 3 through 0 are not implemented and always read 0.Address: 4007_6000h base + 3h offset = 4007_6003hBit 7 6 5 4 3 2 1 0Read SPRF SPMF SPTEF MODF 0WriteReset 0 0 1 0 0 0 0 0SPI0_S field descriptionsField Description7SPRFSPI read buffer full flagSPRF is set at the completion of an SPI transfer to indicate that received data may be read from the SPIdata (D) register. When the receive DMA request is disabled (RXDMAE is 0), SPRF is cleared by readingSPRF while it is set and then reading the SPI data register. When the receive DMA request is enabled(RXDMAE is 1), SPRF is automatically cleared when the DMA transfer for the receive DMA request iscompleted (RX DMA Done is asserted).Table continues on the next page...Chapter 34 Serial Peripheral Interface (SPI)KL04 Sub-Family Reference Manual, Rev. 3.1, November 2012Freescale Semiconductor, Inc. 565
