DMA_DSR_BCRn field descriptionsField Description31ReservedThis field is reserved.This read-only field is reserved and always has the value 0.30CEConfiguration errorAny of the following conditions causes a configuration error:• BCR, SAR, or DAR does not match the requested transfer size.• A value greater than 0F_FFFFh is written to BCR.• Bits 31-20 of SAR or DAR are written with a value other than one of the allowed values. See SARand DAR.• SSIZE or DSIZE is set to an unsupported value.• BCR equals 0 when the DMA receives a start condition.CE is cleared at hardware reset or by writing a 1 to the DONE bit.0 No configuration error exists.1 A configuration error has occurred.29BESBus error on sourceBES is cleared at hardware reset or by writing a 1 to the DONE bit.0 No bus error occurred.1 The DMA channel terminated with a bus error during the read portion of a transfer.28BEDBus error on destinationBED is cleared at hardware reset or by writing a 1 to the DONE bit.0 No bus error occurred.1 The DMA channel terminated with a bus error during the write portion of a transfer.27ReservedThis field is reserved.This read-only field is reserved and always has the value 0.26REQRequest0 No request is pending or the channel is currently active. Cleared when the channel is selected.1 The DMA channel has a transfer remaining and the channel is not selected.25BSYBusy0 DMA channel is inactive. Cleared when the DMA has finished the last transaction.1 BSY is set the first time the channel is enabled after a transfer is initiated.24DONETransactions doneSet when all DMA controller transactions complete as determined by transfer count, or based on errorconditions. When BCR reaches zero, DONE is set when the final transfer completes successfully. DONEcan also be used to abort a transfer by resetting the status bits. When a transfer completes, software mustclear DONE before reprogramming the DMA.0 DMA transfer is not yet complete. Writing a 0 has no effect.1 DMA transfer completed. Writing a 1 to this bit clears all DMA status bits and should be used in aninterrupt service routine to clear the DMA interrupt and error bits.23–0BCRThis field contains the number of bytes yet to be transferred for a given block.Restriction: BCR must be written with a value equal to or less than 0F_FFFFh. After being written with avalue in this range, bits 23-20 of BCR read back as 1110b. A write to BCR of a valueTable continues on the next page...Memory Map and RegistersKL04 Sub-Family Reference Manual, Rev. 3.1, November 2012326 Freescale Semiconductor, Inc.
