The SPI is completely disabled in stop modes where the peripheral bus clock isstopped and internal logic states are not retained. When the CPU wakes from thesestop modes, all SPI register content is reset.Detailed descriptions of operating modes appear in Low Power Mode Options.34.1.3 Block DiagramsThis section includes block diagrams showing SPI system connections, the internalorganization of the SPI module, and the SPI clock dividers that control the master modebit rate.34.1.3.1 SPI System Block DiagramThe following figure shows the SPI modules of two MCUs connected in a master-slavearrangement. The master device initiates all SPI data transfers. During a transfer, themaster shifts data out (on the MOSI pin) to the slave while simultaneously shifting datain (on the MISO pin) from the slave. The transfer effectively exchanges the data that wasin the SPI shift registers of the two SPI systems. The SPSCK signal is a clock outputfrom the master and an input to the slave. The slave device must be selected by a lowlevel on the slave select input (SS pin). In this system, the master device has configuredits SS pin as an optional slave select output.SPI SHIFTERMASTER8 BITSCLOCKGENERATORMOSIMISO MISOMOSISPSCK SPSCKSS SSSLAVESPI SHIFTER8 BITSFigure 34-1. SPI System ConnectionsChapter 34 Serial Peripheral Interface (SPI)KL04 Sub-Family Reference Manual, Rev. 3.1, November 2012Freescale Semiconductor, Inc. 557
