Control and DataWriteReadDMAMemory/PeripheralMemory/PeripheralControl and DataFigure 23-2. Dual-Address TransferAny operation involving a DMA channel follows the same three steps:1. Channel initialization—The transfer control descriptor, contained in the channelregisters, is loaded with address pointers, a byte-transfer count, and controlinformation using accesses from the slave peripheral bus.2. Data transfer—The DMA accepts requests for data transfers. Upon receipt of arequest, it provides address and bus control for the transfers via its master connectionto the system bus and temporary storage for the read data. The channel performs oneor more source read and destination write data transfers.3. Channel termination—Occurs after the operation is finished successfully or due to anerror. The channel indicates the operation status in the channel's DSR, described inthe definitions of the DMA Status Registers (DSRn) and Byte Count Registers(BCRn).Memory Map and RegistersDescriptions of each register and its bit assignments follow. Modifying DMA controlregisters during a transfer can result in undefined operation. The following table showsthe mapping of DMA controller registers. The DMA programming model is accessed viathe slave peripheral bus. The concatenation of the source and destination addressregisters, the status and byte count register, and the control register create a 128-bittransfer control descriptor (TCD) that defines the operation of each DMA channel.23.3Memory Map and RegistersKL04 Sub-Family Reference Manual, Rev. 3.1, November 2012322 Freescale Semiconductor, Inc.
