35.4.1.7 Clock synchronizationBecause wire AND logic is performed on SCL, a high-to-low transition on SCL affectsall devices connected on the bus. The devices start counting their low period and, after adevice's clock has gone low, that device holds SCL low until the clock reaches its highstate. However, the change of low to high in this device clock might not change the stateof SCL if another device clock is still within its low period. Therefore, the synchronizedclock SCL is held low by the device with the longest low period. Devices with shorterlow periods enter a high wait state during this time; see the following diagram. When allapplicable devices have counted off their low period, the synchronized clock SCL isreleased and pulled high. Afterward there is no difference between the device clocks andthe state of SCL, and all devices start counting their high periods. The first device tocomplete its high period pulls SCL low again.S C L 2S ta r t C o u n t in g H ig h P e r io dIn te r n a l C o u n te r R e s e tS C L 1S C LD e la yFigure 35-27. I2C clock synchronization35.4.1.8 HandshakingThe clock synchronization mechanism can be used as a handshake in data transfers. Aslave device may hold SCL low after completing a single byte transfer (9 bits). In thiscase, it halts the bus clock and forces the master clock into wait states until the slavereleases SCL.35.4.1.9 Clock stretchingThe clock synchronization mechanism can be used by slaves to slow down the bit rate ofa transfer. After the master drives SCL low, a slave can drive SCL low for the requiredperiod and then release it. If the slave's SCL low period is greater than the master's SCLChapter 35 Inter-Integrated Circuit (I2C)KL04 Sub-Family Reference Manual, Rev. 3.1, November 2012Freescale Semiconductor, Inc. 605
