• Resides between a crossbar switch slave port and a peripheral bridge bus controller• 2-stage pipeline design matching the AHB system bus protocol• Combinationally passes non-decorated accesses to peripheral bridge bus controller• Conversion of decorated loads and stores from processor core into atomic read-modify-writes• Decorated loads support unsigned bit field extracts, load-and-{set,clear}-1bitoperations• Decorated stores support bit field inserts, logical AND, OR and XOR operations• Support for byte, halfword and word-sized decorated operations• Supports minimum signal toggling on AHB output bus to reduce power dissipation17.1.3 Modes of OperationThe BME module does not support any special modes of operation. As a memory-mapped device located on a crossbar slave AHB system bus port, BME responds basedstrictly on memory addresses for accesses to the connected peripheral bridge buscontroller.All functionality associated with the BME module resides in the core platform's clockdomain; this includes its connections with the crossbar slave port and the PBRIDGE buscontroller.17.2 External Signal DescriptionThe BME module does not directly support any external interfaces.The internal interfaces include two standard AHB buses with 32-bit datapath widths: theprimary input from the appropriate crossbar slave port (mx_h) and the primaryoutput to the PBRIDGE bus controller (sx_h).Note the signal directions are defined by the BME's view and are labeled based on thedominant direction. Accordingly, the mx_h AHB bus is the primary input, eventhough there are certain data phase signals (mx_h{rdata, ready, resp}) which are outputsfrom BME. Likewise, the sx_h AHB bus is the primary output even though thereare specific data phase signals (sx_h{rdata, ready, resp}) which are inputs to BME.Chapter 17 Bit Manipulation Engine (BME)KL04 Sub-Family Reference Manual, Rev. 3.1, November 2012Freescale Semiconductor, Inc. 241
