• Timer 1 creates an interrupt every 5.12 ms.• Timer 3 creates a trigger event every 30 ms.The PIT module must be activated by writing a 0 to MCR[MDIS].The 50 MHz clock frequency equates to a clock period of 20 ns. Timer 1 needs to triggerevery 5.12 ms/20 ns = 256,000 cycles and Timer 3 every 30 ms/20 ns = 1,500,000 cycles.The value for the LDVAL register trigger is calculated as:LDVAL trigger = (period / clock period) -1This means LDVAL1 and LDVAL3 must be written with 0x0003E7FF and 0x0016E35Frespectively.The interrupt for Timer 1 is enabled by setting TCTRL1[TIE]. The timer is started bywriting 1 to TCTRL1[TEN].Timer 3 shall be used only for triggering. Therefore, Timer 3 is started by writing a 1 toTCTRL3[TEN]. TCTRL3[TIE] stays at 0.The following example code matches the described setup:// turn on PITPIT_MCR = 0x00;// Timer 1PIT_LDVAL1 = 0x0003E7FF; // setup timer 1 for 256000 cyclesPIT_TCTRL1 = TIE; // enable Timer 1 interruptsPIT_TCTRL1 |= TEN; // start Timer 1// Timer 3PIT_LDVAL3 = 0x0016E35F; // setup timer 3for 1500000 cyclesPIT_TCTRL3 |= TEN; // start Timer 331.6 Example configuration for chained timersIn the example configuration:• The PIT clock has a frequency of 100 MHz.• Timers 1 and 2 are available.• An interrupt shall be raised every 1 hour.The PIT module needs to be activated by writing a 0 to MCR[MDIS].Chapter 31 Periodic Interrupt Timer (PIT-RTI)KL04 Sub-Family Reference Manual, Rev. 3.1, November 2012Freescale Semiconductor, Inc. 527
