FGPIOx_PTOR field descriptions (continued)Field Description0 Corresponding bit in PDORn does not change.1 Corresponding bit in PDORn is set to the inverse of its existing logic state.37.3.5 Port Data Input Register (FGPIOx_PDIR)Address: Base address + 10h offsetBit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0R PDIWReset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0FGPIOx_PDIR field descriptionsField Description31–0PDIPort Data InputReads 0 at the unimplemented pins for a particular device. Pins that are not configured for a digitalfunction read 0. If the Port Control and Interrupt module is disabled, then the corresponding bit in PDIRdoes not update.0 Pin logic level is logic 0, or is not configured for use by digital function.1 Pin logic level is logic 1.37.3.6 Port Data Direction Register (FGPIOx_PDDR)The PDDR configures the individual port pins for input or output.Address: Base address + 14h offsetBit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0R PDDWReset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0FGPIOx_PDDR field descriptionsField Description31–0PDDPort Data DirectionConfigures individual port pins for input or output.0 Pin is configured as general-purpose input, for the GPIO function.1 Pin is configured as general-purpose output, for the GPIO function.FGPIO memory map and register definitionKL04 Sub-Family Reference Manual, Rev. 3.1, November 2012654 Freescale Semiconductor, Inc.
