RTC_SR field descriptions (continued)Field Description0TIFTime Invalid FlagThe time invalid flag is set on POR or software reset. The TSR and TPR do not increment and read aszero when this bit is set. This bit is cleared by writing the TSR register when the time counter is disabled.0 Time is valid.1 Time is invalid and time counter is read as zero.33.2.7 RTC Lock Register (RTC_LR)Address: 4003_D000h base + 18h offset = 4003_D018hBit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16R 0WReset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0R 0 1 LRL SRL CRL TCL 1WReset 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1RTC_LR field descriptionsField Description31–8ReservedThis field is reserved.This read-only field is reserved and always has the value 0.7ReservedThis field is reserved.This read-only field is reserved and always has the value 1.6LRLLock Register LockAfter being cleared, this bit can be set only by POR or software reset.0 Lock Register is locked and writes are ignored.1 Lock Register is not locked and writes complete as normal.5SRLStatus Register LockAfter being cleared, this bit can be set only by POR or software reset.0 Status Register is locked and writes are ignored.1 Status Register is not locked and writes complete as normal.4CRLControl Register LockAfter being cleared, this bit can only be set by POR.0 Control Register is locked and writes are ignored.1 Control Register is not locked and writes complete as normal.Table continues on the next page...Register definitionKL04 Sub-Family Reference Manual, Rev. 3.1, November 2012548 Freescale Semiconductor, Inc.
