Section number Title Page35.3 Memory map and register descriptions.........................................................................................................................58935.3.1 I2C Address Register 1 (I2Cx_A1)..............................................................................................................59035.3.2 I2C Frequency Divider register (I2Cx_F)....................................................................................................59135.3.3 I2C Control Register 1 (I2Cx_C1)...............................................................................................................59235.3.4 I2C Status register (I2Cx_S)........................................................................................................................59335.3.5 I2C Data I/O register (I2Cx_D)...................................................................................................................59535.3.6 I2C Control Register 2 (I2Cx_C2)...............................................................................................................59635.3.7 I2C Programmable Input Glitch Filter register (I2Cx_FLT).......................................................................59735.3.8 I2C Range Address register (I2Cx_RA)......................................................................................................59835.3.9 I2C SMBus Control and Status register (I2Cx_SMB).................................................................................59935.3.10 I2C Address Register 2 (I2Cx_A2)..............................................................................................................60035.3.11 I2C SCL Low Timeout Register High (I2Cx_SLTH)..................................................................................60135.3.12 I2C SCL Low Timeout Register Low (I2Cx_SLTL)...................................................................................60135.4 Functional description...................................................................................................................................................60135.4.1 I2C protocol.................................................................................................................................................60135.4.2 10-bit address...............................................................................................................................................60735.4.3 Address matching.........................................................................................................................................60835.4.4 System management bus specification........................................................................................................60935.4.5 Resets...........................................................................................................................................................61235.4.6 Interrupts......................................................................................................................................................61235.4.7 Programmable input glitch filter..................................................................................................................61435.4.8 Address matching wakeup...........................................................................................................................61535.4.9 DMA support...............................................................................................................................................61535.5 Initialization/application information...........................................................................................................................616Chapter 36Universal Asynchronous Receiver/Transmitter (UART0)36.1 Introduction...................................................................................................................................................................61936.1.1 Features........................................................................................................................................................619KL04 Sub-Family Reference Manual, Rev. 3.1, November 2012Freescale Semiconductor, Inc. 25
