ADCx_OFS field descriptionsField Description31–16ReservedThis field is reserved.This read-only field is reserved and always has the value 0.15–0OFSOffset Error Correction Value28.3.9 ADC Plus-Side Gain Register (ADCx_PG)The Plus-Side Gain Register (PG) contains the gain error correction for the overallconversion in single-ended mode. PG, a 16-bit real number in binary format, is the gainadjustment factor, with the radix point fixed between ADPG15 and ADPG14. Thisregister must be written by the user with the value described in the calibration procedure.Otherwise, the gain error specifications may not be met.Address: 4003_B000h base + 2Ch offset = 4003_B02ChBit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0R 0 PGWReset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0ADCx_PG field descriptionsField Description31–16ReservedThis field is reserved.This read-only field is reserved and always has the value 0.15–0PGPlus-Side Gain28.3.10 ADC Plus-Side General Calibration Value Register(ADCx_CLPD)The Plus-Side General Calibration Value Registers (CLPx) contain calibrationinformation that is generated by the calibration function. These registers contain sevencalibration values of varying widths: CLP0[5:0], CLP1[6:0], CLP2[7:0], CLP3[8:0],CLP4[9:0], CLPS[5:0], and CLPD[5:0]. CLPx are automatically set when the self-calibration sequence is done, that is, CAL is cleared. If these registers are written by theuser after calibration, the linearity error specifications may not be met.Register definitionKL04 Sub-Family Reference Manual, Rev. 3.1, November 2012434 Freescale Semiconductor, Inc.
