3.7.2 CMP ConfigurationThis section summarizes how the module has been configured in the chip. For acomprehensive description of the module itself, see the module’s dedicated chapter.Signal multiplexingModule signalsRegisteraccessCMPPeripheralbridge 0Other peripheralsFigure 3-22. CMP configurationTable 3-33. Reference links to related informationTopic Related module ReferenceFull description Comparator (CMP) ComparatorSystem memory map System memory mapClocking Clock distributionPower management Power managementSignal multiplexing Port control Signal multiplexing3.7.2.1 CMP Instantiation InformationThe device includes one high speed comparator and two 8-input multiplexors for both theinverting and non-inverting inputs of the comparator. Each CMP input channel connectsto both muxes. Two of the channels are connected to internal sources, leaving resourcesto support up to 6 input pins. See the channel assignment table for a summary of CMPinput connections for this device.The CMP also includes one 6-bit DAC with a 64-tap resistor ladder network, whichprovides a selectable voltage reference for applications where voltage reference is neededfor internal connection to the CMP.The CMP can be optionally on in all modes except VLLS0.The CMP has several module to module interconnects in order to facilitate ADCtriggering, TPM triggering and UART IR interfaces. For complete details on the CMPmodule interconnects please refer to the Module-to-Module section.Chapter 3 Chip ConfigurationKL04 Sub-Family Reference Manual, Rev. 3.1, November 2012Freescale Semiconductor, Inc. 75
