31.3.2 PIT Upper Lifetime Timer Register (PIT_LTMR64H)This register is intended for applications that chain timer 0 and timer 1 to build a 64-bitlifetimer.Address: 4003_7000h base + E0h offset = 4003_70E0hBit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31R LTHWReset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0PIT_LTMR64H field descriptionsField Description0–31LTHLife Timer valueShows the timer value of timer 1. If this register is read at a time t1, LTMR64L shows the value of timer 0at time t1.31.3.3 PIT Lower Lifetime Timer Register (PIT_LTMR64L)This register is intended for applications that chain timer 0 and timer 1 to build a 64-bitlifetimer.To use LTMR64H and LTMR64L, timer 0 and timer 1 need to be chained. To obtain thecorrect value, first read LTMR64H and then LTMR64L. LTMR64H will have the valueof CVAL1 at the time of the first access, LTMR64L will have the value of CVAL0 at thetime of the first access, therefore the application does not need to worry about carry-overeffects of the running counter.Address: 4003_7000h base + E4h offset = 4003_70E4hBit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31R LTLWReset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0PIT_LTMR64L field descriptionsField Description0–31LTLLife Timer valueShows the value of timer 0 at the time LTMR64H was last read. It will only update if LTMR64H is read.Chapter 31 Periodic Interrupt Timer (PIT-RTI)KL04 Sub-Family Reference Manual, Rev. 3.1, November 2012Freescale Semiconductor, Inc. 521
