SW-DPSELECT[31:24] (APSEL) selects the APSELECT[7:4] (APBANKSEL) selects the bankA[3:2] from the APACC selects the registerwithin the bankAHB Access Port(AHB-AP) MDM-APStatus 0x00Control 0x01IDR 0x3F AHB-APSELECT[31:24] = 0x00 selects the AHB-APSee ARM documentation for further detailsMDM-APSELECT[31:24] = 0x01 selects the MDM-APSELECT[7:4] = 0x0 selects the bank with Status and CtrlA[3:2] = 2’b00 selects the Status RegisterA[3:2] = 2’b01 selects the Control RegisterSELECT[7:4] = 0xF selects the bank with IDRA[3:2] = 2’b11 selects the IDR Register(IDR register reads 0x001C_0020)Bus MatrixSee Control and Status RegisterDescriptionsDebug PortInternal BusAccess PortData[31:0] A[7:4] A[3:2] RnWAPSELDecode Debug Port ID Register (IDCODE)Control/Status (CTRL/STAT)AP Select (SELECT)Read Buffer (RDBUFF)DP Registers0x000x040x080x0CData[31:0] A[3:2] RnWDPACCData[31:0] A[3:2] RnWAPACCDebug Port(DP)GenericSee the ARM Debug Interface v5p1 Supplement.Figure 9-1. MDM AP Addressing9.3.1 MDM-AP Control RegisterTable 9-3. MDM-AP Control register assignmentsBit Name Secure1 Description0 Flash Mass Erase in Progress Y Set to cause mass erase. Cleared by hardware after mass eraseoperation completes.When mass erase is disabled (via MEEN and SEC settings), the eraserequest does not occur and the Flash Mass Erase in Progress bitcontinues to assert until the next system reset.1 Debug Disable N Set to disable debug. Clear to allow debug operation. When set itoverrides the C_DEBUGEN bit within the DHCSR and force disablesDebug logic.Table continues on the next page...Chapter 9 DebugKL04 Sub-Family Reference Manual, Rev. 3.1, November 2012Freescale Semiconductor, Inc. 135
