I2Cx_S field descriptions (continued)Field Description• One byte transfer, including ACK/NACK bit, completes if FACK is 0. An ACK or NACK is sent on thebus by writing 0 or 1 to TXAK after this bit is set in receive mode.• One byte transfer, excluding ACK/NACK bit, completes if FACK is 1.• Match of slave address to calling address including primary slave address, range slave address,alert response address, second slave address, or general call address.• Arbitration lost• In SMBus mode, any timeouts except SCL and SDA high timeouts• I2C bus stop detection if the STOPIE bit in the Input Glitch Filter register is 1NOTE: To clear the I2C bus stop detection interrupt: In the interrupt service routine,first clear the STOPF bit in the Input Glitch Filter register by writing 1 to it, andthen clear the IICIF bit. If this sequence is reversed, the IICIF bit is assertedagain.0 No interrupt pending1 Interrupt pending0RXAKReceive Acknowledge0 Acknowledge signal was received after the completion of one byte of data transmission on the bus1 No acknowledge signal detected35.3.5 I2C Data I/O register (I2Cx_D)Address: 4006_6000h base + 4h offset = 4006_6004hBit 7 6 5 4 3 2 1 0Read DATAWriteReset 0 0 0 0 0 0 0 0I2Cx_D field descriptionsField Description7–0DATADataIn master transmit mode, when data is written to this register, a data transfer is initiated. The mostsignificant bit is sent first. In master receive mode, reading this register initiates receiving of the next byteof data.NOTE: When making the transition out of master receive mode, switch the I2C mode before reading theData register to prevent an inadvertent initiation of a master receive data transfer.In slave mode, the same functions are available after an address match occurs.The C1[TX] bit must correctly reflect the desired direction of transfer in master and slave modes for thetransmission to begin. For example, if the I2C module is configured for master transmit but a masterreceive is desired, reading the Data register does not initiate the receive.Reading the Data register returns the last byte received while the I2C module is configured in masterreceive or slave receive mode. The Data register does not reflect every byte that is transmitted on the I2Cbus, and neither can software verify that a byte has been written to the Data register correctly by reading itback.Chapter 35 Inter-Integrated Circuit (I2C)KL04 Sub-Family Reference Manual, Rev. 3.1, November 2012Freescale Semiconductor, Inc. 595
