31.3.6 Timer Control Register (PIT_TCTRLn)These register contain the control bits for each timer.Address: 4003_7000h base + 108h offset + (16d × i), where i=0d to 1dBit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15R 0WReset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0Bit 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31R 0 CHN TIE TENWReset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0PIT_TCTRLn field descriptionsField Description0–28ReservedThis field is reserved.This read-only field is reserved and always has the value 0.29CHNChain ModeWhen activated, Timer n-1 needs to expire before timer n can decrement by 1.Timer 0 can not be changed.0 Timer is not chained.1 Timer is chained to previous timer. For example, for Channel 2, if this field is set, Timer 2 is chained toTimer 1.30TIETimer Interrupt EnableWhen an interrupt is pending, or, TFLGn[TIF] is set, enabling the interrupt will immediately cause aninterrupt event. To avoid this, the associated TFLGn[TIF] must be cleared first.0 Interrupt requests from Timer n are disabled.1 Interrupt will be requested whenever TIF is set.31TENTimer EnableEnables or disables the timer.0 Timer n is disabled.1 Timer n is enabled.Chapter 31 Periodic Interrupt Timer (PIT-RTI)KL04 Sub-Family Reference Manual, Rev. 3.1, November 2012Freescale Semiconductor, Inc. 523
