PMC_LVDSC2 field descriptionsField Description7LVWFLow-Voltage Warning FlagThis read-only status bit indicates a low-voltage warning event. LVWF is set when VSupply transitions belowthe trip point, or after reset and VSupply is already below VLVW. LVWF bit may be 1 after power on reset,therefore, to use LVW interrupt function, before enabling LVWIE, LVWF must be cleared by writingLVWACK first.0 Low-voltage warning event not detected1 Low-voltage warning event detected6LVWACKLow-Voltage Warning AcknowledgeThis write-only bit is used to acknowledge low voltage warning errors. Write 1 to clear LVWF. Readsalways return 0.5LVWIELow-Voltage Warning Interrupt EnableEnables hardware interrupt requests for LVWF.0 Hardware interrupt disabled (use polling)1 Request a hardware interrupt when LVWF = 14–2ReservedThis field is reserved.This read-only field is reserved and always has the value 0.1–0LVWVLow-Voltage Warning Voltage SelectSelects the LVW trip point voltage (VLVW). The actual voltage for the warning depends on LVDSC1[LVDV].00 Low trip point selected (VLVW = VLVW1)01 Mid 1 trip point selected (VLVW = VLVW2)10 Mid 2 trip point selected (VLVW = VLVW3)11 High trip point selected (VLVW = VLVW4)14.5.3 Regulator Status And Control register (PMC_REGSC)The PMC contains an internal voltage regulator. The voltage regulator design uses abandgap reference that is also available through a buffer as input to certain internalperipherals, such as the CMP and ADC. The internal regulator provides a status bit(REGONS) indicating the regulator is in run regulation.NOTEThis register is reset on Chip Reset Not VLLS and by resettypes that trigger Chip Reset not VLLS. See the Reset sectionfor more information.Memory map and register descriptionsKL04 Sub-Family Reference Manual, Rev. 3.1, November 2012214 Freescale Semiconductor, Inc.
