3.8.2.4 PIT/DAC TriggersPIT Channel 0 is configured as the DAC hardware trigger source. For more details, referto DAC chapter.3.8.3 Low-power timer configurationSignal multiplexingRegisteraccessPeripheralbridgeModule signalsLow-power timerFigure 3-25. LPT configurationTable 3-40. Reference links to related informationTopic Related module ReferenceFull description Low-power timer Low-power timerSystem memory map System memory mapClocking Clock DistributionPower management Power managementSignal Multiplexing Port control Signal Multiplexing3.8.3.1 LPTMR Instantiation InformationThe low-power timer (LPTMR) allows operation during all power modes. The LPTMRcan operate as a real-time interrupt or pulse accumulator. It includes a 15-bit prescaler(real-time interrupt mode) or glitch filter (pulse accumulator mode).The LPTMR can be clocked from the internal reference clock, the internal 1 kHz LPO,OSCERCLK, or an external 32.768 kHz crystal. In VLLS0 mode, the clocking option islimited to an external pin with the OSC configured for bypass (external clock) operation.An interrupt is generated (and the counter may reset) when the counter equals the valuein the 16-bit compare register.Chapter 3 Chip ConfigurationKL04 Sub-Family Reference Manual, Rev. 3.1, November 2012Freescale Semiconductor, Inc. 81
