FGPIO memory map (continued)Absoluteaddress(hex)Register name Width(in bits) Access Reset value Section/pageF80F_F044 Port Set Output Register (FGPIOB_PSOR) 32W(alwaysreads 0)0000_0000h 37.3.2/652F80F_F048 Port Clear Output Register (FGPIOB_PCOR) 32W(alwaysreads 0)0000_0000h 37.3.3/653F80F_F04C Port Toggle Output Register (FGPIOB_PTOR) 32W(alwaysreads 0)0000_0000h 37.3.4/653F80F_F050 Port Data Input Register (FGPIOB_PDIR) 32 R 0000_0000h 37.3.5/654F80F_F054 Port Data Direction Register (FGPIOB_PDDR) 32 R/W 0000_0000h 37.3.6/65437.3.1 Port Data Output Register (FGPIOx_PDOR)This register configures the logic levels that are driven on each general-purpose outputpins.Address: Base address + 0h offsetBit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0R PDOWReset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0FGPIOx_PDOR field descriptionsField Description31–0PDOPort Data OutputUnimplemented pins for a particular device read as zero.0 Logic level 0 is driven on pin, provided pin is configured for general-purpose output.1 Logic level 1 is driven on pin, provided pin is configured for general-purpose output.37.3.2 Port Set Output Register (FGPIOx_PSOR)This register configures whether to set the fields of the PDOR.Address: Base address + 4h offsetBit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0R 0W PTSOReset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0FGPIO memory map and register definitionKL04 Sub-Family Reference Manual, Rev. 3.1, November 2012652 Freescale Semiconductor, Inc.
