SPI0_S field descriptions (continued)Field Description0 No data available in the receive data buffer1 Data available in the receive data buffer6SPMFSPI match flagSPMF is set after SPRF is 1 when the value in the receive data buffer matches the value in the M register.To clear the flag, read SPMF when it is set and then write a 1 to it.0 Value in the receive data buffer does not match the value in the M register1 Value in the receive data buffer matches the value in the M register5SPTEFSPI transmit buffer empty flagThis bit is set when the transmit data buffer is empty. When the transmit DMA request is disabled(TXDMAE is 0), SPTEF is cleared by reading the S register with SPTEF set and then writing a data valueto the transmit buffer at D. The S register must be read with SPTEF set to 1 before writing data to the Dregister; otherwise, the D write is ignored. When the transmit DMA request is enabled (TXDMAE is 1),SPTEF is automatically cleared when the DMA transfer for the transmit DMA request is completed (TXDMA Done is asserted). SPTEF is automatically set when all data from the transmit buffer transfers intothe transmit shift register. For an idle SPI, data written to D is transferred to the shifter almost immediatelyso that SPTEF is set within two bus cycles, allowing a second set of data to be queued into the transmitbuffer. After completion of the transfer of the data in the shift register, the queued data from the transmitbuffer automatically moves to the shifter, and SPTEF is set to indicate that room exists for new data in thetransmit buffer. If no new data is waiting in the transmit buffer, SPTEF simply remains set and no datamoves from the buffer to the shifter.If a transfer does not stop, the last data that was transmitted is sent out again.0 SPI transmit buffer not empty1 SPI transmit buffer empty4MODFMaster mode fault flagMODF is set if the SPI is configured as a master and the slave select input goes low, indicating someother SPI device is also configured as a master. The SS pin acts as a mode fault error input only whenMSTR is 1, MODFEN is 1, and SSOE is 0; otherwise, MODF will never be set. MODF is cleared byreading MODF while it is 1 and then writing to the SPI control register 1 (C1).0 No mode fault error1 Mode fault error detected3–0ReservedThis field is reserved.This read-only field is reserved and always has the value 0.34.3.5 SPI data register (SPIx_D)This register is both the input and output register for SPI data. A write to the registerwrites to the transmit data buffer, allowing data to be queued and transmitted.When the SPI is configured as a master, data queued in the transmit data buffer istransmitted immediately after the previous transmission has completed.Memory Map and Register DescriptionsKL04 Sub-Family Reference Manual, Rev. 3.1, November 2012566 Freescale Semiconductor, Inc.
