33.2.3 RTC Time Alarm Register (RTC_TAR)Address: 4003_D000h base + 8h offset = 4003_D008hBit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0R TARWReset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0RTC_TAR field descriptionsField Description31–0TARTime Alarm RegisterWhen the time counter is enabled, the SR[TAF] is set whenever the TAR[TAR] equals the TSR[TSR] andthe TSR[TSR] increments. Writing to the TAR clears the SR[TAF].33.2.4 RTC Time Compensation Register (RTC_TCR)Address: 4003_D000h base + Ch offset = 4003_D00ChBit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0R CIC TCV CIR TCRWReset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0RTC_TCR field descriptionsField Description31–24CICCompensation Interval CounterCurrent value of the compensation interval counter. If the compensation interval counter equals zero thenit is loaded with the contents of the CIR. If the CIC does not equal zero then it is decremented once asecond.23–16TCVTime Compensation ValueCurrent value used by the compensation logic for the present second interval. Updated once a second ifthe CIC equals 0 with the contents of the TCR field. If the CIC does not equal zero then it is loaded withzero (compensation is not enabled for that second increment).15–8CIRCompensation Interval RegisterConfigures the compensation interval in seconds from 1 to 256 to control how frequently the TCR shouldadjust the number of 32.768 kHz cycles in each second. The value written should be one less than thenumber of seconds. For example, write zero to configure for a compensation interval of one second. Thisregister is double buffered and writes do not take affect until the end of the current compensation interval.7–0TCRTime Compensation RegisterConfigures the number of 32.768 kHz clock cycles in each second. This register is double buffered andwrites do not take affect until the end of the current compensation interval.Table continues on the next page...Register definitionKL04 Sub-Family Reference Manual, Rev. 3.1, November 2012544 Freescale Semiconductor, Inc.
