The mode fault flag is cleared automatically by a read of the SPI Status Register (withMODF set) followed by a write to SPI Control Register 1. If the mode fault flag iscleared, the SPI becomes a normal master or slave again.34.4.9 Low Power Mode OptionsThis section describes the low power mode options.34.4.9.1 SPI in Run ModeIn run mode, with the SPI system enable (SPE) bit in the SPI control register clear, theSPI system is in a low-power, disabled state. SPI registers can still be accessed, butclocks to the core of this module are disabled.34.4.9.2 SPI in Wait ModeSPI operation in wait mode depends upon the state of the SPISWAI bit in SPI ControlRegister 2.• If SPISWAI is clear, the SPI operates normally when the CPU is in wait mode.• If SPISWAI is set, SPI clock generation ceases and the SPI module enters a powerconservation state when the CPU is in wait mode.• If SPISWAI is set and the SPI is configured for master, any transmission andreception in progress stops at wait mode entry. The transmission and receptionresumes when the SPI exits wait mode.• If SPISWAI is set and the SPI is configured as a slave, any transmission andreception in progress continues if the SPSCK continues to be driven from themaster. This keeps the slave synchronized to the master and the SPSCK.If the master transmits data while the slave is in wait mode, the slave continuesto send data consistent with the operation mode at the start of wait mode (that is,if the slave is currently sending its SPIx_D to the master, it continues to send thesame byte. Otherwise, if the slave is currently sending the last data received bytefrom the master, it continues to send each previously received data from themaster byte).Chapter 34 Serial Peripheral Interface (SPI)KL04 Sub-Family Reference Manual, Rev. 3.1, November 2012Freescale Semiconductor, Inc. 579
