LPTMRx_CSR field descriptions (continued)Field Description01 Pulse counter input 1 is selected.10 Pulse counter input 2 is selected.11 Pulse counter input 3 is selected.3TPPTimer Pin PolarityConfigures the polarity of the input source in Pulse Counter mode. TPP must be changed only when theLPTMR is disabled.0 Pulse Counter input source is active-high, and the CNR will increment on the rising-edge.1 Pulse Counter input source is active-low, and the CNR will increment on the falling-edge.2TFCTimer Free-Running CounterWhen clear, TFC configures the CNR to reset whenever TCF is set. When set, TFC configures the CNR toreset on overflow. TFC must be altered only when the LPTMR is disabled.0 CNR is reset whenever TCF is set.1 CNR is reset on overflow.1TMSTimer Mode SelectConfigures the mode of the LPTMR. TMS must be altered only when the LPTMR is disabled.0 Time Counter mode.1 Pulse Counter mode.0TENTimer EnableWhen TEN is clear, it resets the LPTMR internal logic, including the CNR and TCF. When TEN is set, theLPTMR is enabled. While writing 1 to this field, CSR[5:1] must not be altered.0 LPTMR is disabled and internal logic is reset.1 LPTMR is enabled.32.3.2 Low Power Timer Prescale Register (LPTMRx_PSR)Address: 4004_0000h base + 4h offset = 4004_0004hBit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16R 0WReset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0R 0 PRESCALE PBYP PCSWReset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0Memory map and register definitionKL04 Sub-Family Reference Manual, Rev. 3.1, November 2012534 Freescale Semiconductor, Inc.
