DMA_SARn field descriptionsField Description31–0SAREach SAR contains the byte address used by the DMA controller to read data. The SARn is typicallyaligned on a 0-modulo-ssize boundary—that is, on the natural alignment of the source data.Restriction: Bits 31-20 of this register must be written with one of only four allowed values. Each ofthese four allowed values corresponds to a valid region of the device's memory map. Theallowed values are:• 0x000x_xxxx• 0x1FFx_xxxx• 0x200x_xxxx• 0x400x_xxxxAfter being written with one of the allowed values, bits 31-20 read back as the written value.After being written with any other value, bits 31-20 read back as an indeterminate value.23.3.2 Destination Address Register (DMA_DARn)RestrictionFor this register:• Only 32-bit writes are allowed. 16-bit and 8-bit writesresult in a bus error.• Only four values are allowed to be written to bits 31-20 ofthis register. A write of any other value to these bits causesa configuration error when the channel starts to execute.For more information about the configuration error, see thedescription of the CE field of DSR.Address: 4000_8000h base + 104h offset + (16d × i), where i=0d to 3dBit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0R DARWReset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0DMA_DARn field descriptionsField Description31–0DAREach DAR contains the byte address used by the DMA controller to write data. The DARn is typicallyaligned on a 0-modulo-dsize boundary—that is, on the natural alignment of the destination data.Restriction: Bits 31-20 of this register must be written with one of only four allowed values. Each ofthese four allowed values corresponds to a valid region of the device's memory map. Theallowed values are:• 0x000x_xxxx• 0x1FFx_xxxx• 0x200x_xxxx• 0x400x_xxxxMemory Map and RegistersKL04 Sub-Family Reference Manual, Rev. 3.1, November 2012324 Freescale Semiconductor, Inc.
