the transmit shifter, then write 0 and then write 1 to the UART_C2[TE] bit. This actionqueues an idle character to be sent as soon as the shifter is available. As long as thecharacter in the shifter does not finish whileUART_C2[TE] is cleared, the UARTtransmitter never actually releases control of the UART_TX pin.The length of the break character is affected by the UART_S2[BRK13], UART_C1[M]and UART_C4[M10] bits as shown below.Table 36-27. Break character lengthBRK13 M M10 SBNS Break characterlength0 0 0 0 10 bit times0 0 0 1 11 bit times0 1 0 0 11 bit times0 1 0 1 12 bit times0 X 1 0 12 bit times0 X 1 1 13 bit times1 0 0 0 13 bit times1 0 0 1 14 bit times1 1 0 0 14 bit times1 1 0 1 15 bit times1 X 1 0 15 bit times1 X 1 1 16 bit times36.3.3 Receiver functional descriptionIn this section, the receiver block diagram is a guide for the overall receiver functionaldescription. Next, the data sampling technique used to reconstruct receiver data isdescribed in more detail. Finally, two variations of the receiver wakeup function areexplained.The receiver input is inverted by setting UART_S2[RXINV]. The receiver is enabled bysetting the UART_C2[RE] bit. Character frames consist of a start bit of logic 0, eight toten data bits (msb or lsb first), and one or two stop bits of logic 1. For information about9-bit or 10-bit data mode, refer to 8-bit, 9-bit and 10-bit data modes. For the remainder ofthis discussion, assume the UART is configured for normal 8-bit data mode.After receiving the stop bit into the receive shifter, and provided the receive data registeris not already full, the data character is transferred to the receive data register and thereceive data register full (UART_S1[RDRF]) status flag is set. If UART_S1[RDRF] wasalready set indicating the receive data register (buffer) was already full, the overrun (OR)Functional descriptionKL04 Sub-Family Reference Manual, Rev. 3.1, November 2012638 Freescale Semiconductor, Inc.
