is provided from the LPTMR. The LPTMR triggering output is always enabled when theLPTMR is enabled. The first signal is supplied to enable the CMP and DAC and isasserted at the same time as the TCF flag is set. The delay to the second signal thattriggers the CMP to capture the result of the compare operation is dependent on theLPTMR configuration. In Time Counter mode with prescaler enabled, the delay is 1/2Prescaler output period. In Time Counter mode with prescaler bypassed, the delay is 1/2Prescaler clock period.The delay between the first signal from LPTMR and the second signal from LPTMRmust be greater than the Analog comparator initialization delay as defined in the devicedatasheet.Timers3.8.1 Timer/PWM Module ConfigurationThis section summarizes how the module has been configured in the chip. For acomprehensive description of the module itself, see the module’s dedicated chapter.Signal multiplexingModule signalsRegisteraccessTPMPeripheral buscontroller 0Other peripheralsFigure 3-23. TPM configurationTable 3-35. Reference links to related informationTopic Related module ReferenceFull description Timer/PWM Module Timer/PWM ModuleSystem memory map System memory mapClocking Clock distributionPower management Power managementSignal multiplexing Port control Signal multiplexing3.8Chapter 3 Chip ConfigurationKL04 Sub-Family Reference Manual, Rev. 3.1, November 2012Freescale Semiconductor, Inc. 77
