NOTEThe reset value of this register depends on the reset source:• POR (including LVD) — 0x82• LVD (without POR) — 0x02• VLLS mode wakeup due to RESET pin assertion — 0x41• VLLS mode wakeup due to other wakeup sources — 0x01• Other reset — a bit is set if its corresponding reset sourcecaused the resetAddress: 4007_F000h base + 0h offset = 4007_F000hBit 7 6 5 4 3 2 1 0Read POR PIN WDOG 0 LOC LVD WAKEUPWriteReset 1 0 0 0 0 0 1 0RCM_SRS0 field descriptionsField Description7PORPower-On ResetIndicates a reset has been caused by the power-on detection logic. Because the internal supply voltagewas ramping up at the time, the low-voltage reset (LVD) status bit is also set to indicate that the resetoccurred while the internal supply was below the LVD threshold.0 Reset not caused by POR1 Reset caused by POR6PINExternal Reset PinIndicates a reset has been caused by an active-low level on the external RESET pin.0 Reset not caused by external reset pin1 Reset caused by external reset pin5WDOGWatchdogIndicates a reset has been caused by the watchdog timer Computer Operating Properly (COP) timing out.This reset source can be blocked by disabling the COP watchdog: write 00 to the SIM's COPC[COPT]field.0 Reset not caused by watchdog timeout1 Reset caused by watchdog timeout4–3ReservedThis field is reserved.This read-only field is reserved and always has the value 0.2LOCLoss-of-Clock ResetIndicates a reset has been caused by a loss of external clock. The MCG clock monitor must be enabledfor a loss of clock to be detected. Refer to the detailed MCG description for information on enabling theclock monitor.0 Reset not caused by a loss of external clock.1 Reset caused by a loss of external clock.Table continues on the next page...Reset memory map and register descriptionsKL04 Sub-Family Reference Manual, Rev. 3.1, November 2012234 Freescale Semiconductor, Inc.
