I2Cx_SMB field descriptions (continued)Field Description4TCKSELTimeout Counter Clock SelectSelects the clock source of the timeout counter.0 Timeout counter counts at the frequency of the bus clock / 641 Timeout counter counts at the frequency of the bus clock3SLTFSCL Low Timeout FlagThis bit is set when the SLT register (consisting of the SLTH and SLTL registers) is loaded with a non-zerovalue (LoValue) and an SCL low timeout occurs. Software clears this bit by writing a logic 1 to it.NOTE: The low timeout function is disabled when the SLT register's value is zero.0 No low timeout occurs1 Low timeout occurs2SHTF1SCL High Timeout Flag 1This read-only bit sets when SCL and SDA are held high more than clock × LoValue / 512, which indicatesthe bus is free. This bit is cleared automatically.0 No SCL high and SDA high timeout occurs1 SCL high and SDA high timeout occurs1SHTF2SCL High Timeout Flag 2This bit sets when SCL is held high and SDA is held low more than clock × LoValue/512. Software clearsthis bit by writing a 1 to it.0 No SCL high and SDA low timeout occurs1 SCL high and SDA low timeout occurs0SHTF2IESHTF2 Interrupt EnableEnables SCL high and SDA low timeout interrupt.0 SHTF2 interrupt is disabled1 SHTF2 interrupt is enabled35.3.10 I2C Address Register 2 (I2Cx_A2)Address: 4006_6000h base + 9h offset = 4006_6009hBit 7 6 5 4 3 2 1 0Read SAD 0WriteReset 1 1 0 0 0 0 1 0I2Cx_A2 field descriptionsField Description7–1SADSMBus AddressTable continues on the next page...Memory map and register descriptionsKL04 Sub-Family Reference Manual, Rev. 3.1, November 2012600 Freescale Semiconductor, Inc.
