12.2.8 System Clock Gating Control Register 4 (SIM_SCGC4)Address: 4004_7000h base + 1034h offset = 4004_8034hBit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16R 1 0 0SPI00CMP0 0WReset 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0R 0 0 0 0UART0 0 0I2C01 0WReset 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0SIM_SCGC4 field descriptionsField Description31–28ReservedThis field is reserved.This read-only field is reserved and always has the value 1.27–24ReservedThis field is reserved.This read-only field is reserved and always has the value 0.23ReservedThis field is reserved.This read-only field is reserved and always has the value 0.22SPI0SPI0 Clock Gate ControlThis bit controls the clock gate to the SPI0 module.0 Clock disabled1 Clock enabled21–20ReservedThis field is reserved.This read-only field is reserved and always has the value 0.19CMPComparator Clock Gate ControlThis bit controls the clock gate to the comparator module.0 Clock disabled1 Clock enabled18ReservedThis field is reserved.This read-only field is reserved and always has the value 0.17–14ReservedThis field is reserved.This read-only field is reserved and always has the value 0.13ReservedThis field is reserved.This read-only field is reserved and always has the value 0.12ReservedThis field is reserved.This read-only field is reserved and always has the value 0.Table continues on the next page...Memory map and register definitionKL04 Sub-Family Reference Manual, Rev. 3.1, November 2012176 Freescale Semiconductor, Inc.
