13.4.2.2 Stop mode exit sequenceExit from a low-power stop mode is initiated either by a reset or an interrupt event. Thefollowing sequence then executes to restore the system to a run mode (RUN or VLPR):1. The on-chip regulator in the PMC and internal power switches are restored.2. Clock generators are enabled in the MCG.3. System and bus clocks are enabled to all masters and slaves.4. The CPU clock is enabled and the CPU begins servicing the reset or interrupt thatinitiated the exit from the low-power stop mode.13.4.2.3 Aborted stop mode entryIf an interrupt or a reset occurs during a stop entry sequence, the SMC can abort thetransition early and return to RUN mode without completely entering the stop mode. Anaborted entry is possible only if the reset or interrupt occurs before the PMC begins thetransition to stop mode regulation. After this point, the interrupt or reset is ignored untilthe PMC has completed its transition to stop mode regulation. When an aborted stopmode entry sequence occurs, the SMC's PMCTRL[STOPA] is set to 1.13.4.2.4 Transition to wait modesFor wait modes (WAIT and VLPW), the CPU clock is gated off while all other clockingcontinues, as in RUN and VLPR mode operation. Some modules that support stop-in-wait functionality have their clocks disabled in these configurations.13.4.2.5 Transition from stop modes to Debug modeThe debugger module supports a transition from STOP, WAIT, VLPS, and VLPW backto a Halted state when the debugger has been enabled, that is, ENBDM is 1. As part ofthis transition, system clocking is re-established and is equivalent to the normal RUN andVLPR mode clocking configuration.13.4.3 Run modesThe device contains two different run modes:• Run• Very Low-Power Run (VLPR)Chapter 13 System Mode Controller (SMC)KL04 Sub-Family Reference Manual, Rev. 3.1, November 2012Freescale Semiconductor, Inc. 201
